LATCH CONTROL CIRCUIT, SEMICONDUCTOR MEMORY DEVICE AND DATA PROCESSING DEVICE

摘要

PROBLEM TO BE SOLVED: To stabilize latch operation. SOLUTION: A latch control circuit consists of a transfer MOS (62) of an n-channel MOS transistor and a latch circuit (DBL) which latches data which are transmitted from a logic circuit disposed in a stage before the transfer MOS 62 via the transfer MOS. In this case, when data is taken to the latch circuit via the transfer MOS 62, the power source voltage (VCCW) on the high potential side of the latch circuit (DBL) is set lower than that of the logic circuit to stabilize the latch operation, without increasing the layout area of the latch circuit, and the externally supplied voltage can be lowered.