NON-VOLATILE SEMICONDUCTOR STORAGE

摘要

PROBLEM TO BE SOLVED: To prevent a wiring error when a voltage being applied to a bit line and a selection gate line lowers on an STI is used. SOLUTION: First, a voltage, for example, 3 V is applied to a Vbit 2, a voltage, for example, 5 V is applied to Vsg1, and a voltage Vdif is transferred to the diffusion layer of a memory cell. In this case, Vcg1-Vcg4 are simultaneously set to 5 V or the line, and all diffusion layers of the memory cell and a channel part are set to Vdif. Before the voltages Vcg1-Vcg4 of word lines WL1-WL4 are increased to 10 V or 20 V, the voltage Vsg1 of a selection gate line SG1 is decreased to 2 V, thus preventing the charge of Vdif from passing through the bit line via a selection transistor QS1 and hence preventing potential from being decreased.