发明名称 |
EXTRA REGISTER MINIMIZES CPU IDLE CYCLES DURING CACHE REFILL |
摘要 |
A CPU has an execution unit for operating on data under instruction control. A cache and a buffer register are coupled in parallel to an input of the execution unit. The buffer register supplies an information item, such as data or an instruction, to the execution unit upon the cache having completed a refill process.
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申请公布号 |
WO9932979(A1) |
申请公布日期 |
1999.07.01 |
申请号 |
WO1998IB01549 |
申请日期 |
1998.10.05 |
申请人 |
KONINKLIJKE PHILIPS ELECTRONICS N.V.;PHILIPS AB |
发明人 |
SIMOVICH, SLOBODAN;ELTMAN, BRAD |
分类号 |
G06F9/38;G06F12/08;(IPC1-7):G06F12/08;G06F9/30 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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