| 摘要 |
A dividing circuit comprises a plurality (N) of transistor stages connected in a ring. Each stage comprises a first pair of transistors of a first conductivity type (T1,T2) connected in series between a first voltage level (Vdd) and an output node (O1), a second pair of transistors of a second conductivity type (T3,T4) connected in series between a second voltage level and said output node (O1), wherein control nodes of a first transistor (T1,T4) of each said transistor pair are connected together to provide an input node (I1) for the stage, and control nodes of a second transistor (T2,T3) of each said transistor pair are connected together to provide a clock node (CLK IN) for the stage, wherein the input node of each stage is connected to the output node of a preceding stage whereby an output signal is generated at each of said output nodes, each cycle of the output signal representing N cycles of a clock signal applied to said clock nodes of the stages, the output signal having a duty cycle that is closer to 50% than the duty cycle of said clock signal. |
