| 摘要 |
PCT No. PCT/JP96/02016 Sec. 371 Date May 9, 1997 Sec. 102(e) Date May 9, 1997 PCT Filed Jul. 19, 1996 PCT Pub. No. WO97/04328 PCT Pub. Date Feb. 6, 1997A memory fail analysis device for a semiconductor test system is attained in which fail data of a plurality of bits is read out in parallel to count the overall fail bits in a short period of time. In a fail bit counting device in a fail memory for the semiconductor memory test system, a fail memory block 358 is provided which is recognized as a single memory when measuring the MUT while divided into M blocks to read the stored data in M bits parallel at the same time when counting the number of fail bits. Further, a fail counter 360 is provided which receives the M bit data and encodes the number of either high or low logic levels in the data into binary code data and counts the binary code data to accumulate the counted number.
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