发明名称 |
Low power set associative cache memory |
摘要 |
A four-way cache data memory is provided, having a cache data RAM (30) and a tag RAM (28). The tag RAM (28) is enabled to access one of the tags therein. This tag is compared with the tag portion of the received memory address to determine if a tag is stored therein. If a true comparison results, a HIT is indicated and this is utilized to enable a portion of the cache data RAM (30). The data in the enabled portion is then output on the data bus.
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申请公布号 |
US5913223(A) |
申请公布日期 |
1999.06.15 |
申请号 |
US19930008206 |
申请日期 |
1993.01.25 |
申请人 |
SHEPPARD, DOUGLAS PARKS;LAU, WILLIAM |
发明人 |
SHEPPARD, DOUGLAS PARKS;LAU, WILLIAM |
分类号 |
G06F12/08;(IPC1-7):G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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