发明名称 MULTI-BIT COMPARING CIRCUIT AND MEMORY
摘要 PROBLEM TO BE SOLVED: To enable high-speed operation by providing an exclusive OR circuit, calculating and inputting the wired-OR logic of its output to a decision circuit and outputting a signal indicating a match or mismatch, and suppressing the potential of a wired-OR node by using a potential suppressing circuit. SOLUTION: When one of 1-bit comparing circuits SG1 to SGn finds that input data Din matches comparison data Dcp, a current flows to a transistors Q1 or Q3 connected to a node Na in each of other 1-bit comparing circuits having found mismatches and a current (i) is drawn from the node Na. When a mismatch is one bit, a current flowing to the base-side diode D1 of a transistor Q11 in a decision device 10 becomes i+ia=ti/4 obtained by adding a current ia(=i/4) flowing to a transistor Q13 to the drawn current (i). The potential at the node Na becomes lower than that at a node Nb by a forward potential difference based upon the difference in current density between the two diodes D1 and D2.
申请公布号 JPH11149366(A) 申请公布日期 1999.06.02
申请号 JP19970318054 申请日期 1997.11.19
申请人 HITACHI LTD 发明人 NISHIYAMA MASAHIKO;HIGETA KEIICHI
分类号 G06F7/04;G11C15/04;(IPC1-7):G06F7/04 主分类号 G06F7/04
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