| 摘要 |
<p>A free loop oscillator system including a set of successive delay elements (12, 14, 16, 18, 20) forming a free loop oscillator, a set of taps (34, 36, 38, 40) disposed between the delay elements, a circuit (28, 32) for determining the speed of the free running loop oscillator, and circuit (32, 42, 43) for choosing a given tap in response to the speed of the free running loop oscillator. Such a system may be implemented as part of an interval timer, a printer controller, a frequency synthesizer, an FM modulator, a digital-to-analog converter, or any other device which requires the availability of finely addressable signals.</p> |
