| 摘要 |
An output buffer (100; 200) in accordance with the present invention exhibits a fixed output signal slew rate. The output signal behavior is independent of the capacitive load (CL) seen by the buffer. The circuit includes a capacitive feedback path from the output node to circuitry which drives the output transistors. In one embodiment, the feedback path comprises two capacitive elements (CFP, CFN), one which comes into play during a rising edge transition and the other which affects a falling edge transition. In a second embodiment, a single capacitive element (CF) is coupled to a switching circuit (P4, N4) for use during either a falling transition or a rising transition. The second embodiment provides precharging of the output transistor gates, and so improves response time.
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