METHOD FOR CALCULATING DELAY TIME IN PROPAGATION OF LOGIC CIRCUIT

摘要

A method for calculating delay time in propagation of logic circuit by which the delay time of a logic circuit can be calculated accurately even when the capacity of the input terminal of the cell of the logic circuit varies depending upon the rounded waveform edge of an applied signal. While the delay time has been calculated by considering that the capacity of the input terminal of the cell is fixed in the conventional delay time calculating method, the delay time is calculated by taking the capacity variation of the input terminal caused by the rounded waveform edge of the input signal into account, by providing the capacity of the input terminal in a delay library as the function of the rounded waveform edge in this method. In this method, in addition, the delay time of each logic circuit candidate solution is used for a comparative object, as a basis for selecting the optimum solution from a plurality of logic circuit candidate solutions for realizing a desired logical function.