| 发明名称 |
A buffering integrated circuit |
| 摘要 |
<p>A buffering integrated circuit with a buffering means which receives a shifted down voltage at one of its inputs from a MOSFET. With the aid of a second MOSFET, the buffering means provides an output voltage which is substantially equal to its input voltage prior to level shift down. <IMAGE></p> |
| 申请公布号 |
EP0913932(A2) |
申请公布日期 |
1999.05.06 |
| 申请号 |
EP19980308565 |
申请日期 |
1998.10.20 |
| 申请人 |
XEROX CORPORATION |
发明人 |
MCINTYRE, HARRY J.;YAZDY, MOSTAFA R. |
| 分类号 |
H03K19/0185;H03F3/345;H03F3/347;H03F3/50;(IPC1-7):H03F3/50 |
主分类号 |
H03K19/0185 |
| 代理机构 |
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代理人 |
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| 地址 |
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