| 摘要 |
A device and method for generating a refresh signal for use in a dynamic memory having an array of memory cells organized according to addresses, the device including a refresh data memory array, a write driver circuit responsive to a refresh signal and timing information for writing at least a portion of the timing information in the refresh data memory array according to addresses corresponding to addresses used in the array of memory cells, a circuit for reading the written timing information from the refresh data memory array corresponding to certain of the addresses, and a logic circuit responsive to the present value of the timing information and said read timing information for producing said refresh signal indicative of when a refresh is required.
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