发明名称 Test circuit for integrated circuit on same chip
摘要 The test circuit has a data writer for delivery of M-bit data that are split into N and written to a memory. From it the N of the M-bit data are read-out by a function director. One N is transmitted to an input/output terminal, and the M-bit data are compared with a prepared, expected M-bit value. The comparison result is determined and a coupled wide data bus transmits the N between the data writer, memory, and function director
申请公布号 DE19818045(A1) 申请公布日期 1999.03.25
申请号 DE19981018045 申请日期 1998.04.22
申请人 MITSUBISHI ELECTRIC SYSTEM LSI DESIGN CORP., ITAMI, HYOGO, JP;MITSUBISHI DENKI K.K., TOKIO/TOKYO, JP 发明人 TOKI, HIDEKI, ITAMI, HYOGO, JP;SHIROSHIMA, KIYOYUKI, ITAMI, HYOGO, JP;KITAGUCHI, AKIRA, TOKIO/TOKYO, JP;HATAKENAKA, MAKOTO, TOKIO/TOKYO, JP;MATSUO, MASAAKI, ISAHAYA, NAGASAKI, JP;SAITOH, TSUYOSHI, ISAHAYA, NAGASAKI, JP
分类号 G01R31/28;G06F11/22;G11C11/413;G11C29/10;G11C29/34;G11C29/36;G11C29/38;G11C29/56;(IPC1-7):G11C29/00 主分类号 G01R31/28
代理机构 代理人
主权项
地址
您可能感兴趣的专利