METHOD AND SYSTEM FOR INPUT/OUTPUT CONTROL IN A MULTIPROCESSOR SYSTEM UTILIZING SIMULTANEOUS VARIABLE-WIDTH BUS ACCESS

摘要

A method and system for input/output control in a multiprocessor system having multiprocessors coupled to a system memory via a common wide bus. The common wid e bus is subdivided into multiple sub-buses which may be accessed individually or in groups by a selected processor, or individual sub-buses may be accessed by multiple pro cessors simultaneously in response to one or more transfer requests. In response to a tr ansfer request having a data address associated therewith, a particular target device i s identified. The data address is then written into an address queue. Thereafter, one or more of the multiple sub-buses are utilized to transfer data to or from a single processor i n response to a transfer request from a single processor. In response to a transfer request from multiple processors, one or more of the multiple sub-buses may be utilized separ ately to simultaneously transfer data to or from multiple processors.