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经营范围
发明名称
METHOD AND APPARATUS FOR ZERO LATENCY BUS TRANSACTIONS
摘要
A split transaction bus in a computer system that permits out-of-order replies in a pipelined manner using an additional bus for use in the response phase.
申请公布号
WO9832063(A3)
申请公布日期
1999.03.18
申请号
WO1997US22147
申请日期
1997.12.03
申请人
INTEL CORPORATION
发明人
JAYAKUMAR, MUTHURAJAN;HUANG, SUNNY, C.;MACWILLIAMS, PETER, D.;WU, WILLIAM, S.;PAWLOWSKI, STEPHEN;PRASAD, BINDI, A.
分类号
G06F13/37;G06F13/42
主分类号
G06F13/37
代理机构
代理人
主权项
地址
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