| 摘要 |
According to a novel pattern layout of a full CMOS SRAM cell comprising first and second transfer, driver, and load transistors, six in total, the driver and load transistors are parallel to a buried word line. The first transfer transistor and the first driver transistor are alongside and parallel to one complementary data line and the second transfer transistor and the second driver transistor are alongside and parallel to the other complementary data line. Moreover, a power bus and a reference bus are parallel to and on both sides of each of the complementary data lines. Preferably, four gate electrodes of the first and second driver and load transistors are individually formed while the word line is used gate electrodes of the first and second transfer transistors. |
