| 摘要 |
<p>The invention relates to a configuration having two internal clock systems in a synchronous DRAM memory circuit such that an external clock signal (CLK) is transferred to a switch (S1) to a first internal clock system (1) that generates a signal for controlling the output. Further, in case the switch (S1) is off, a switch (S2) is on such that the internal clock system (1) enters to a reset state and the internal clock system (2) is in the stand-by state. Next, when the /CAS signal is received the internal clock system (2) can operate it any time in accordance with the external clock signal CLK. As a result, the control of a burst data transfer operation is carried out from the internal clock system (2). <IMAGE></p> |
