发明名称 PLL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To quickly shift the output of a VCO to a target frequency by opening a PLL loop until an output frequency of the VCO reaches the target frequency and outputting a fixed pump up signal or pump down signal. SOLUTION: When a control circuit 21 is set to a frequency that is higher than a present state by a frequency change key 20, the circuit 21 supervises that a comparison result from a 2nd phase phase comparator 7 changes from delay to progress (state where a pump up signal is changes to a pump down signal) from and that the comparison result from the comparator 7 changes from progress to delay when it is set to a frequency that is lower than the present state. And when it detects the change, it gives an L level signal to an inverter 9 and also resets a flip-flop 10 for up. With this, after this, 5th and 6th NAND circuits 16 and 17 output signals based on a comparison result of a 1st phase comparator 5 and a PLL loop is under closed control.
申请公布号 JPH1174788(A) 申请公布日期 1999.03.16
申请号 JP19970232387 申请日期 1997.08.28
申请人 SANYO ELECTRIC CO LTD;TOTTORI SANYO ELECTRIC CO LTD 发明人 WASHIMI IKUAKI
分类号 H03L7/18;H03L7/087 主分类号 H03L7/18
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