Verfahren zur Programmierung von Redundanzregistern in einer Zeilenredundanzschaltung für einen Halbleiterspeicherbaustein

摘要

A method for programming non-volatile row redundancy memory registers (RR1-RR4) each one associated to a respective pair of redundancy row and each one programmable to store in two subsets (1,2;1,2') of a set of memory cells (MC0-MC9) a pair of addresses of a respective pair of adjacent defective rows; each memory register is supplied with row address signals (R0-R9) and with a respective selection signal (C0-C3) belonging to a set of column address signals (CABUS); the method provides for: applying to the row address signals (R0-R9) the address of a first defective row of the pair of adjacent defective rows; activating one of the selection signals (C0-C3) for selecting the memory register which is to be programmed; applying to a further column address signal (C4) a first logic level to select for programming, in the selected memory register, a first subset (1,2) of memory cells (MC0-MC9); enabling the programming of the address of the first defective row of the pair of adjacent defective rows into the first subset (1,2) of memory cells; applying to at least a subset (R0-R3) of the row address signals (R0-R9) the address of the second defective row of the pair; applying to the further column address signal (C4) a second, opposite logic level to select for programming, in the selected memory register (RR1-RR4), at least a group (2') of memory cells (MC0-MC3) of the second subset (1,2') of the two subsets (1,2;1,2') of memory cells; enabling the programming of the address of the second defective row of the pair of adjacent defective rows into the second subset (1,2') of memory cells.