| 摘要 |
A semiconductor device testing apparatus is provided which includes an output voltage corrective circuit wherein a test voltage to be applied to a semiconductor under test (DUT) 14 is corrected through digital processing. An offset memory 1, a gain memory 2, an output level register 3, a tester processor 5, a selection register 15, a selector 16, a data register 17, an all-pin data setting sequencer 19, a load controller 20, a digital multiplier 21, and a digital adder 22 are provided in the main frame of the testing apparatus. A multi-channel D/A converter 23 for converting digital serial data from the main frame to analog parallel data for each channel and drivers 13 each for applying the test voltage to one of the pins of the DUT 14 are provided in the test head of the testing apparatus. The offset memory 1 prestores therein offset data contained in correction data and the gain memory gain data also contained in the correction data. The output level register 3 stores therein the test voltage to be applied to the pin of the DUT for each channel. |
