| 摘要 |
PROBLEM TO BE SOLVED: To reduce pattern area and to reduce waveform distortion and noise by providing a CPU for controlling the operation of an entire transmitter and a field programmable logic array(FPLA) for controlling the respective constitutive circuits of the transmitter under the control of the CPU. SOLUTION: Each control circuit is composed of the FPGA. A source oscillating clock from an oscillator 3 is supplied through an FPGA 41 to an LSI and by providing a gate at the source oscillating clock to be inputted to the FPGA 41, control is performed for stopping the operating clock of the LSI according to an external control signal. Thus, the operation of all the LSI is stopped and power consumption can remarkably be reduced. Further, since more gates can be secured per package area in comparison with a discrete IC, the required package area can be reduced and since a signal line pattern between the respective circuits is wired inside the FPGA, the pattern area can be reduced. |
