发明名称 ATM CONTROLLER AND ATM COMMUNICATION CONTROLLER USING THE SAME
摘要 <p>PROBLEM TO BE SOLVED: To cope with the setting and change in a protocol processing and to reduce the loads of a software processing and a memory capacity by forming the data block of a fixed length by assembling received data cells on a buffer memory and instructing a transfer, corresponding to the transmission and reception of the cells for one data block. SOLUTION: Packet data are transferred between a memory 5 inside a terminal 1 and a buffer memory 40 by the unit of the data block of the fixed length, and the transfer is performed corresponding to the transmission and reception of the cells for one data block. Thus, in this ATM controller 8, the inexpensive memory of a small capacity can be used as the buffer memory 40. Also by limiting an ATM protocol processing, of which an MPU 100 is in charge limiting only to a processing for which it is desired to be provided with flexibility in the change of processing contents and performing the other processings by wired logic, the processing loads of the MPU 100 are reduced and the ATM controller 8 of a low cost and low power consumption is realized.</p>
申请公布号 JPH1117694(A) 申请公布日期 1999.01.22
申请号 JP19970170363 申请日期 1997.06.26
申请人 HITACHI LTD 发明人 YOKOYAMA TATSUYA;MIZUTANI MIKA;TAKADA OSAMU;HATA EIZO
分类号 H04L29/02;H04L12/951;H04Q3/00;(IPC1-7):H04L12/28 主分类号 H04L29/02
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