发明名称 |
An error variance circuit |
摘要 |
A circuit has the reproduced error as detected at an error detect circuit (35) added to the image signal of the input signal picture element of n bits, and further has the variance output signal converted into a signal of m (</=n-1) bits to output on the display panel. The error detect circuit (35) has a clear circuit (42) that clears the error at every frame. This reduces to zero the prior error for every frame thus preventing excessive noise from preceding frames and non-image duration to avoid flickering of picture. <IMAGE> |
申请公布号 |
AU701010(B2) |
申请公布日期 |
1999.01.21 |
申请号 |
AU19950037858 |
申请日期 |
1995.11.14 |
申请人 |
FUJITSU GENERAL LIMITED |
发明人 |
MASAYUKI KOBAYASHI;MASAMICHI NAKAJIMA;ASAO KOSAKAI;JUNICHI ONODERA;HAYATO DENDA |
分类号 |
G02F1/133;G09G3/20;G09G3/28;G09G3/36 |
主分类号 |
G02F1/133 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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