| 摘要 |
<p>Array of electrically programmable non-volatile memory cells, each cell comprising a floating gate (9;90), a control gate (12;120) coupled to a row (WL) of the array, a first electrode (7,13;70;130) associated with a column (BL1-BL8) of the array and a second electrode (6;70) separated from the first electrode by a channel region underlying said floating gate, the first electrode, the second electrode and the channel region being formed in a layer of semiconductor material (5) of a first conductivity type and having a second conductivity type, comprising at least one ROM memory cell (2;200) which is identical to the electrically programmable non-volatile memory cells and is associated with a respective row and a respective column of the array, the ROM cell (2;200) comprising means for allowing or not allowing the electrical separation between said respective column and the second electrode (6';61) of the ROM cell (2;200), if the ROM cell must store a first logic state or, respectively, a second logic state. <IMAGE> <IMAGE></p> |
