发明名称 |
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE |
摘要 |
A semiconductor integrated circuit device which has a word line, a pair of bit lines, an information storing capacitor and an N-channel MOSFET whose gate is connected to the word line and which has a source/drain passage between one of the pair of bit lines and one of the terminals of the information storing capacitor on a semiconductor substrate and is operated on a positive power supply voltage and the ground potential of the circuit. A positive bias voltage higher than the ground potential of the circuit is generated and supplied to a P-type well region in which the MOSFET for the selection of the addresses of dynamic memory cells is formed as a bias voltage.
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申请公布号 |
WO9900846(A1) |
申请公布日期 |
1999.01.07 |
申请号 |
WO1998JP02620 |
申请日期 |
1998.06.15 |
申请人 |
HITACHI, LTD.;TADAKI, YOSHITAKA;ITOU, YUTAKA |
发明人 |
TADAKI, YOSHITAKA;ITOU, YUTAKA |
分类号 |
G11C11/4076;G11C11/4097;H01L27/02;H01L27/105;H01L27/108;(IPC1-7):H01L27/108;H01L21/824 |
主分类号 |
G11C11/4076 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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