| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a clock signal control method capable of easily generating a multiplied clock without using a loop configuration at high speed and being used as a variable delay circuit by dividing the external clock into clocks of multiple phases and taking the intermediate timing of respective phases. SOLUTION: The external clock 1 is divided into the clocks 3 is multiple phases. The input timing difference of the different phase pulse edges of the multiphase clocks 3 which are frequency-divided is divided. Namely, a frequency divider 2 frequency-divides the outer clock 1 into the clocks 3 of multiple phases. A multiphase clock multiplication circuit 5 has timing difference dividers 4a dividing the pulses different phases of the different phase clocks in the multiphase clocks 3 into (n), timing difference dividers 4a dividing the pulse of the same phase into (n) and multiplex circuits 4b multiplexing the pulses 9c of the different phases which are divided into (n). The clocks 9a of the multiple phases are outputted. A clock synthesis circuit 8 synthesizes the multiphase clocks 9a and generates the clock 9b of a single phase.</p> |
