| 摘要 |
A high frequency analog-to-digital converter in which a memory stage receives the result of a series of comparisons of an analog input voltage Vin with a set of reference voltages Vi (where i=0 to Q). Each memory cell Mi (where i=0 to Q) comprises N memory flip-flops L0, L1, . . . LN-1, a multiplexer Mx, and a logic or control module CL. All of the data inputs of the memory flip-flops L0, L1, . . . LN-1 are connected together to the data input of the memory cell. The jth memory flip-flop (where j=0 to N-1) receives at its clock input the clock signal which has been delayed by means of a delay cell having a delay of j.T/N, where T is the period of the clock signal. The data outputs of the N memory flip-flops are connected to the N data inputs of the multiplexer, whose P control inputs receive the P outputs of the control module so that the multiplexer supplies the output signal of the jth memory flip-flop Lj at its output during each (j+1)th fraction of the period T/N. The structure of the memory cells makes it possible to minimize the influence of metastability phenomena, which may give rise to errors during latching of the analog output signals of the comparators.
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