发明名称 Distribution network switch for very large gigabit switching architecture
摘要 An inventive switch for transporting information cells without cell contention is described. The switch includes at least one parallel distribution network. Each distribution network includes an NxN first routing network for receiving cells at a plurality of input ports, where N equals the number the input ports. Illustratively, the routing network is self-routing and non-blocking, such as a Banyan Network. Connected to the NxN network are rho k groups of shared buffers for storing the cells routed through the network for a period of time not greater than one cell cycle, where k is incremented from 1 to [log2N/log2 rho ]-1 and rho equals a predetermined speed-up factor. In one aspect of this embodiment, the number of shared buffers is simply equal to N/ rho . To prevent cell contention and cell loss, all of the contentious cells (cells destined for the same output during the same cycle) are stored in the same shared buffer. Connected to the shared buffers are rho k groups of (N/ rho k)x(N/ rho k) routing networks each having a plurality of output ports for outputting the cells, stored in the shared buffers, based on the destination addresses of each cell. Due in part to the utilization of rho k groups of shared buffers, a large reduction in both hardware costs and chip real estate is realized. Specifically, a decrease in the number of switching stages is achieved.
申请公布号 US5856977(A) 申请公布日期 1999.01.05
申请号 US19970856557 申请日期 1997.05.15
申请人 YANG, MUH-RONG;MA, GIN-KOU 发明人 YANG, MUH-RONG;MA, GIN-KOU
分类号 H04L12/56;(IPC1-7):H04L12/28 主分类号 H04L12/56
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