| 摘要 |
PCT No. PCT/JP96/00037 Sec. 371 Date Sep. 8, 1997 Sec. 102(e) Date Sep. 8, 1997 PCT Filed Dec. 10, 1996 PCT Pub. No. WO97/25719 PCT Pub. Date Jul. 17, 1997It is to provide a test pattern generator that can easily generate expected value data for arbitrary initial values when testing a memory device having a function of write enable/disable control per bit. The pattern generator includes an XOR controller (131) which generates a control signal in response to instructions from an instruction memory (112), an AND gate which receives an output signal of the XOR controller (131) at its one terminal and an inverted output signal of a data generator B (15) at its other input terminal, and an exclusive OR gate (121) which receives an output of the AND gate (123) at its one input terminal and an output a data generator A (14) at the other input terminal.
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