Test pattern generator circuit for integrated circuits and components

摘要

The circuit inputs test pattern data from a data store (2) to a parallel-to-serial converter circuit (3), typically using data with N = 8 words having m = 3 bits. The parallel-to-serial converter circuit can be controlled by a mode control signal (MC), which changes operation between a serial output mode and a parallel serial output mode. In the serial output mode, the data for each word for each connection element for each test cycle are prepared in serial form. In the latter the data are supplied in parallel data for n = 2 words for each connection element (m x n bits), for each test cycle. The pattern storage device is a synchronous dynamic RAM chip (SDRAM), while the cache memory comprises two static RAM chips.