Circuit for generating an internal clock for data output buffers in a synchronous DRAM devices

摘要

An internal clock generating circuit for data output buffers of a synchronous DRAM device, which produces an internal clock with reference to either the positive edge or the negative edge of the system clock CLK by comparing the reference time tCLref(OH) for insuring a low level time tCL of the system clock CLK and output hold time tOH, and which can sufficiently insure the data output setup time tOS and data output hold time tOH regardless of the frequency of the system clock by making the generation points of the internal clock to be varied depending on the frequency of the system clock.