发明名称 |
Method for reducing via inductance in an electronic assembly and article |
摘要 |
A method of making a low inductance conductive via in a laminated substrate by providing a first conductive layer. A first dielectric layer is formed on the first conductive layer. A second conductive layer is formed on the first dielectric layer. A first conductive path is formed in the first conductive layer extending along a first route between a first node and a second node. A first conductive blind-via is connected to the first conductive path at the second node, with the first-blind via being formed in the first dielectric layer at the second node. Lastly, a second conductive path is formed in the second conductive layer that is connected to the first blind via. The second conductive path extends between a third node and the first blind via along a second route. The second route corresponds identically to at least a portion of the first route.
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申请公布号 |
US5841075(A) |
申请公布日期 |
1998.11.24 |
申请号 |
US19980014885 |
申请日期 |
1998.01.28 |
申请人 |
W. L. GORE & ASSOCIATES, INC. |
发明人 |
HANSON, DAVID A. |
分类号 |
H01L23/12;H01L21/48;H01L23/498;H01L23/538;H01L23/66;H05K1/11;(IPC1-7):H05K1/00 |
主分类号 |
H01L23/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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