| 摘要 |
An on-chip voitage multiplier circuit, comprising N serially arranged stages wherein each stage includes a switch Tj (j=1 . . . N), having an upper pin and a lower pin, to the upper pin of which the lower pin of a capacitor Ci (i=1 . . . N) is serially connected, said capacitor also having a lower pin and an upper pin; the intermediate node between each switch Tj (j=1 . . . N) and each capacitor Ci (i=1 . . . N) is connected to the ground voltage Vss through a respective switch Si (i=1 . . . N) and the upper pin of each capacitor Ci (i=1 . . . N) is connected to the supply voltage Vdd through a switch Di (i=1 . . . N); and the lower pin of the switch (T11) of the first stage is directly connected to the supply voltage Vdd and the upper pin of the capacitor (CN) of the last stage is connected to the output pin through an additional switch (T(N+1)).
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