| 摘要 |
A memory device includes an array of memory cells arranged in rows and columns. A row-address decoder allows a row address to propagate therethrough while a row address strobe is at an inactive logic level. In response to a transition of the row address strobe from the inactive level to an active level, the decoder enables a row of memory cells selected by the row address. A row-address latch stores the row address in response to the transition of the row address strobe. The memory device may also include a transition detector that monitors the row address for a transition thereof. A delay circuit is coupled to the decoder, the latch, and the detector. If the monitor detects a transition of the row address, the delay circuit delays the enabling of the row of memory cells and the storing of the row address at least predetermined time after such a transition. Alternatively, the memory device may include a row decoder that is coupled between the latch and the array, and enables a row of memory cells identified by the row address. A control circuit is coupled to the array, receives the row address strobe, and enables the array to output additional data from the identified row even when the row address strobe is at the inactive level. Furthermore, the memory device may include both the control circuit and the row decoder that allows the row address to propagate therethrough while the row address strobe is at an inactive level.
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