Semiconductor integrated circuit device having multi-port RAM memory with random logic portion which can be tested without additional test circuitry

摘要

Multi-port RAM having a RAM core and signal transfer circuit transforming a predetermined signal between the RAM core and a random logic portion. The signal transfer circuit includes a scan path circuit. The scan path circuit for an address signal (ASCAN0), a scan path circuit for a data input signal (DSCAN0) and a selector circuit (ASEL) are provided on the write side, and no scan path circuit is provided on the read side. A read address is supplied through selector circuits (FSEL 2 and RSEL2) termed read address supply device provided on the read side. Thus, reduction of the test circuit allows area reduction of a chip and cost cutting in a semiconductor integrated circuit.