发明名称 |
Multi-level conduction structure for VLSI circuits |
摘要 |
This invention deals with the formation of the multi-level electrode metal structure and the interconnecting inter-level metal studs used in the fabrication of VLSI circuits. After the metal layers have been formed the inter-level dielectric material used in forming the structure is etched away leaving an air dielectric between the levels. The electrode metal and the inter-level metal studs are coated with a thin envelope oxide and the entire structure is covered with a passivation layer using material with a poor step coverage. The structure of this invention provides reduced parasitic capacitance, better step coverage in interconnecting layers, and improved circuit performance.
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申请公布号 |
US5828121(A) |
申请公布日期 |
1998.10.27 |
申请号 |
US19960668518 |
申请日期 |
1996.06.27 |
申请人 |
UNITED MICROELECTRONICS CORPORATION |
发明人 |
LUR, WATER;WU, JIUNN YUAN |
分类号 |
H01L21/768;H01L23/522;H01L23/532;(IPC1-7):H01L23/485;H01L23/535;H01L29/41 |
主分类号 |
H01L21/768 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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