发明名称 |
Microprocessor-based data processing apparatus that commences a next overlapping cycle when a ready signal is detected not to be active |
摘要 |
A data processing technique with which a CPU core accesses memory devices over a bus. Some of the memory devices are on-chip, and some may be off-chip. In order to optimize its operation, the CPU core accesses the on-chip devices via a core buffer interface unit ("BIU") which has been tuned to on-chip operation. Off-chip devices communicate with the CPU core via a system BIU which translates the on-chip bus transactions to meet the off-chip device requirements.
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申请公布号 |
US5822779(A) |
申请公布日期 |
1998.10.13 |
申请号 |
US19970821416 |
申请日期 |
1997.03.21 |
申请人 |
NATIONAL SEMICONDUCTOR CORPORATION |
发明人 |
INTRATER, GIDEON;FALIK, OHAD;OSTRER, AHARON;BAYDATCH, YAIR;SANDBANK, ALBERTO |
分类号 |
G06F13/42;G06F15/78;(IPC1-7):G06F13/18 |
主分类号 |
G06F13/42 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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