发明名称 |
Analog-digital converter capable of reducing a conversion error of an output signal |
摘要 |
A majority logic circuit is supplied with output values of adjacent three comparators. The majority logic circuit outputs, as an output signal, the supplied three output values including at least two equal output values. Inverter circuits and AND circuits produce and output a read signal of an encoder which is a logical product between the output signal and an inverted signal of the output signal.
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申请公布号 |
US5818380(A) |
申请公布日期 |
1998.10.06 |
申请号 |
US19970824549 |
申请日期 |
1997.03.25 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
ITO, MASAO;MIKI, TAKAHIRO;HOSOTANI, SHIRO |
分类号 |
H03M1/10;H03K19/23;H03M1/06;H03M1/36;(IPC1-7):H03M1/36 |
主分类号 |
H03M1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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