High-speed asynchronous memory with current-sensing sense amplifiers

摘要

A high-speed current-sensing amplifier using process-insensitive matching of devices to determine the state of a bistable SRAM cell. The benefits include small voltage swings on heavily capacitively loaded bit lines and bit line bars during memory sensing, thereby maximizing the speed of the SRAM device. One embodiment uses a negative feedback amplifier minimize the bit line and bit line bar voltage swings while sensing current through matched PMOS transistors. Another embodiment uses cascoded PMOS devices to limit the swing of the bit lines and bit line bars, and a supply voltage and process-compensated voltage reference source to set the common-mode voltage of matched resistive sense elements. In all cases power on and off circuitry minimize the power of the memory device.