| 摘要 |
In a nonvolatile semiconductor memory device, upon receiving a defective cell address detection signal HIT, the read-out potential node (VSA NODE 1, VSA NODE 2) and the reference potential node (VREF NODE 1, VREF NODE 2) are equalized to shorten the read-out time required for reading the redundancy memory cell. Furthermore, in a nonvolatile semiconductor memory device having an ATD circuit, the equalizing times of the read-out potential node and the reference potential node are separately set to shorten the read-out time required for reading the main memory cell. With these features, there is overcome a disadvantage in prior art that the read-out time required for reading the redundancy memory cell is longer than the read-out time required for reading the main memory cell due to the slow rising of the HIT signal for detecting the defective cell address.
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