发明名称 Output multiplexer circuit for input/output block
摘要 A input/output circuit (IOB) within an integrated circuit (IC) device, the output signal driving circuitry of the input/output device contains a dedicated multiplexer on the output path wherein a first and second output signal can be time multiplexed on a single output pad. The multiplexer can also be configured to perform as a high speed gate to realize AND, OR, XOR, and XNOR functions. Within an input/output circuit of a programmable integrated circuit, the system provides a dedicated multiplexer that can select between one of two output signals for sending over the single output pad of the IC device. In lieu of using a programmable memory cell as the select control for the dedicated multiplexer, the system allows a number of lines, including an output clock signal, to be the select control. By using the output clock as the select control, the data signals can be effectively time multiplexed over a single output pad and referenced by the output clock. This output multiplexer circuit effectively doubles the number of output signals the IC device can provide with a given number of output pads. The dedicated multiplexer when configured as a high speed gate is useful for generating very high speed system level reset or enable signals or any logic function.
申请公布号 US5811985(A) 申请公布日期 1998.09.22
申请号 US19970783389 申请日期 1997.01.31
申请人 发明人
分类号 H03K19/173;H03K19/177;(IPC1-7):H03K19/173 主分类号 H03K19/173
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