发明名称 |
Parallel processing redundancy scheme for faster access times and lower die area |
摘要 |
A parallel processing redundancy memory circuit. The circuit includes parallel data paths for regular memory columns and redundant columns. An input/output buffer is coupled to the parallel paths and receives I/O selection bits. In operation, address drivers simultaneously access both the regular memory and the redundant columns. The input/output buffer then selects the appropriate data path, as determined by the I/O selection bits, for writing or reading data.
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申请公布号 |
US5808946(A) |
申请公布日期 |
1998.09.15 |
申请号 |
US19970826241 |
申请日期 |
1997.03.27 |
申请人 |
MICRON TECHNOLOGY, INC. |
发明人 |
ROOHPARVAR, FRANKIE FARIBORZ |
分类号 |
G11C29/00;(IPC1-7):G01C7/00 |
主分类号 |
G11C29/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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