| 摘要 |
PROBLEM TO BE SOLVED: To provide a clock generating PLL circuit in which a phase shift of a clock signal is improved without the need for adjusting the range in phase control of the clock signal even when the operating condition is changed. SOLUTION: A phase comparator 1 compares a phase of a reference signal with that of a signal to be compared to provide an output of a control voltage. The control voltage is given to an LPF 2 and a VCO 3, from which a clock signal is generated. A frequency divider 4 frequency-divides the clock signal. An inverter 6 inverts the clock signal and the inverted clock is given to a DFF 7. An output of the frequency divider 4 is given to the DFF 7 and driven by the clock signal from the inverter 6. An output of the frequency divider 4 is given to an input terminal (a) of a changeover circuit 8 and an output of the DFF 7 is given to an input terminal (b). The changeover circuit 8 outputs them selectively and the result is fed to the phase comparator 1 as a signal to be compared. |
