| 摘要 |
<p>PROBLEM TO BE SOLVED: To perform accurately verifying operation for all memory cells. SOLUTION: First, levels ofϕpre,ϕaev are made 'L' at the time of verifying operation, a common bit line 5 and all bit lines BL0-BLm are charged individually to pre-charge voltage Vpre. After that, a level ofϕaev is made 'H', a common bit line 5 is connected to all bit lines BL0-BLm and a sense amplifier 8, and all word lines WL0-WLn are selected by a row decoder circuit 2. And as a memory cell not yet erased exists in a memory cell array 1, it is monitored that the common bit line 5 is discharged and an output signal OUT of the sense amplifier 8 is made 'L'. In this case, as discharge of the common bit lines 5 occurs whenever one memory cell transistor MT not yet erased exits in the memory cell array 1, verifying operation for all memory cells can be performed accurately and en bloc.</p> |
