| 摘要 |
A method of creating an STC structure, used for high density, DRAM designs, has been developed. The process consists of creating a saw-toothed topography for the top surface of a polysilicon storage node electrode. The saw-toothed topography is obtained by placing intrinsic HSG polysilicon spots on an underlying doped polysilicon layer. Thermal oxidation creates thick silicon oxide regions in areas of exposed doped polysilicon, while thinner silicon oxide regions form in areas in which the intrinsic HSG polysilicon spots are oxidized. Removal of both thick and thinner silicon oxide regions, creates the saw-toothed topography in the polysilicon storage node electrode, resulting in surface area, and capacitance increases.
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