| 摘要 |
PROBLEM TO BE SOLVED: To provide a DMA circuit of particlable level which is made small- sized in circuit scale as far as possible and able to perform a high-speed process even if the data bus width increases. SOLUTION: Input data is inputted to a clock-synchronous input buffer 1 first. Then a single rotary barrel shifter 2 which holds data of the bus width makes a shift in byte units according to the difference between the read address of transfer source and the write address of a transfer destination and writes the result in succeeding-stage buffers 30 to 34 for successive transfer. The shift quantity is determined by a data position in the data bus width specified as the address of the transfer destination and in this case, the data transfer is burst transfer of up to four times, so the buffers 30 , and 34 among 30 to 34 are used to hold effective data in relation with the shift quantity; and these buffers are selected by selectors 4 and 5 to output the data. |
