| 摘要 |
PROBLEM TO BE SOLVED: To form a common contact region constituting a static memory as designed by substantially planarizing the upper surface of an isolation region. SOLUTION: A gate electrode 106 is formed in an isolation region on a substrate 101 through a source 103, a drain 104 and a gate insulator 105 and an interlayer insulation layer 108 is formed on a gate electrode interconnection 107 formed on a filed oxide 102 while extending close to the end part thereof. The filed oxide 102 is deposited by recess LOCOS and the substrate 101 is projected inward but substantially planarized on the upper part thereof. When a resist pattern 109 is formed on the interlayer insulation layer 108 with an opening being provided through photolithography, a reflected light from the end part of the electrode interconnection 107 is reflected directly above. Consequently, a common contact region 110 having a desired opening size can be formed by removing the interlayer insulation layer 108 selectively by etching. |
