发明名称 SYSTEM
摘要 PROBLEM TO BE SOLVED: To provide a system which is provided with a PLL circuit that surely and also stably generates a clock signal which synchronizes with a clock signal that is externally supplied. SOLUTION: This system compares a clock signal that is supplied from an external terminal with an internal clock signal through a phase comparator 1, charges it up with a charge pump circuit 2 or forms discharge current in accordance with the output and drives a filter capacity 3. It controls the oscillation frequency of a voltage controlled oscillator 4 through holding voltage of the filter capacity 3 and is provided with a PLL circuit that includes a frequency dividing circuit which forms the internal clock signal based on an oscillating output. In such cases, a voltage detection circuit which detects that the holding voltage of the filter capacity 3 is made prescribed voltage or more and a function which forcedly lowers the holding voltage of the capacity 3 to prescribed potential through a detection output of such a voltage detection circuit are added.
申请公布号 JPH10190454(A) 申请公布日期 1998.07.21
申请号 JP19970319106 申请日期 1997.11.05
申请人 HITACHI LTD 发明人 KURITA KOZABURO
分类号 H03L7/093 主分类号 H03L7/093
代理机构 代理人
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