发明名称 |
Power supply circuit |
摘要 |
A resistor is inserted between the gate of an FET and a feedback winding to produce a delay in a voltage applied to the gate of the FET in comparison with a voltage of the feedback winding due to the influence of an input capacitance existing at the gate of the FET. Thus, a current does not flow before a drain voltage of the FET reaches zero volt, thereby making it possible to reduce the switching loss. <IMAGE> |
申请公布号 |
EP0853372(A1) |
申请公布日期 |
1998.07.15 |
申请号 |
EP19970122781 |
申请日期 |
1997.12.23 |
申请人 |
MATSUSHITA ELECTRIC WORKS, LTD. |
发明人 |
TAMURA, HIDEKI;ABE, HIDEAKI |
分类号 |
H02J7/10;H02M3/338;H02M7/537 |
主分类号 |
H02J7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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