Data reproducing method and data reproducing unit

摘要

A sampler (1) samples an inputted base band signal in accordance with a sampling clock, and holds a sample value (Sn). Delay circuits (7, 8) hold sample values (Sn-1, Sn-2), respectively. A decision circuit (2) determines the sample value (Sn-1), and outputs data (dn-1). A constant multiplier (16) multiplies the data (dn -1) by a constant ( alpha ). A subtracter (17) subtracts the data (dn-1) from the sample value (Sn-1). Another subtracter (13) subtracts the sample value (Sn) from the sample value (Sn-2). A multiplier (14) multiplies the output of the subtracter (17) by that of the subtracter (13), and outputs a timing error signal. A low-pass filter (15) extracts a low frequency component of the timing error signal, and supplies a control voltage to a voltage controlled oscillator (6). The voltage controlled oscillator (6) outputs a sampling clock having a frequency which depends on the control voltage.